Analog demultiplexing

ABSTRACT

The analog demultiplexer (FIG.  6 ) includes an input amplifier (A 1 ), and output amplifiers (AMP 1 –AMP N ). The output and inverting (−) input of amplifiers (AMP 1 –AMP N ) are connected by a respective capacitor (C 1 –C N ). Switches (S 1a , S 1b , etc.) connect the output of amplifier (A 1 ) to the inverting input of one of (AMP 1 –AMP N ). Switches (S 2a , S 2b , etc.) connect the output of one of (AMP 1 –AMP N ) to the non-inverting input of the amplifier A 1 . Switches (S 2a , S 2b , etc.) and (S 1a , S 1b , etc.) open and close together in pairs. With feedback from the output of (AMP 1 –AMP N ) through (A 1 ), the gain and any offset of (AMP 1 –AMP N ) is divided down by the gain of (A 1 ). Amplifier (A 1 ) has capacitors (C S1  and C S2 ) connected to its inputs. Switch (S 50 ) connects the inverting input of amplifier (A 1 ) to its output, and switch (S 40 ) connects the non-inverting input of (A 1 ) to a voltage reference (V REF ) matching (V REF ) applied to (AMP 2 ). Switches (S 30 ) and (S 35 ) connect (C S1 ) and (C S2 ) to the demultiplexer input ( 2 ). In operation, switches (S 40 , S 50 , S 30  and S 35 ) are initially closed, while switches (S 2a , S 2b , etc.) are open to charge both capacitors (C S1 ) and (C S2 ) and the inputs and output of (A 1 ) to (V REF ). Switch (S 50 ) provides feedback to divide down gain errors and offset of (A 1 ). Switches (S 30 , S 35 , S 40  and S 50 ) are then open, while one of switches (S 2a , S 2b , etc.) is closed with one switch (S 1a , S 1b , etc) to drive one of the output voltages (V OUT1 –V OUTN ). With inputs and outputs of (A 1 ) and the connected (AMP 1 –AMP N ) initially be at (V REF ), very little settling time is needed.

CLAIM OF PRIORITY

This application is a continuation of U.S. patent application Ser. No.10/236,340, filed Sep. 5, 2002 (now allowed) now U.S. Pat. No.6,897,800, which claims priority under 35 U.S.C. § 119(e) to U.S.Provisional Patent Application No. 60/317,482, filed Sep. 5, 2001.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following applications, each of whichis incorporated herein by reference:

U.S. patent application Ser. No. 10/236,211, entitled “A SimplifiedMulti-Output Digital to Analog Converter (DAC) For a Flat PanelDisplay,” filed on Sep. 5, 2002 (now U.S. Pat. No. 6,781,532).

U.S. patent application Ser. No. 10/896,275, entitled “A SimplifiedMulti-Output Digital to Analog Converter (DAC) For a Flat PanelDisplay,” filed on Jul. 21, 2004 (now allowed).

BACKGROUND

1. Technical Field

The present invention relates to analog demultiplexer for distributingsignals from a single input line to one of multiple output lines. Inparticular, the present invention relates to an analog demultiplexer fordistributing a video input signal to one of several video display columndrivers, with the analog demultiplexer having minimal offset due to itsamplifiers, and having a minimal amplifier settling time.

2. Related Art

FIG. 1 shows one conventional configuration for an analog demultiplexer.The analog demultiplexer allows a multiplexed analog input voltageV_(IN) received at input 2 to be demultiplexed using a switch S₁ toprovide an output voltage V_(OUT1)–V_(OUTN) at a respective one ofoutputs 4 ₁–4 _(N). The logic control driving switch S₁ toggles switchS₁ to direct an input voltage V_(IN) to one specific output bufferAMP₁–AMP_(N). In this way, an input voltage provided at input V_(IN) canbe demultiplexed to one of numerous output buffers AMP₁–AMP_(N).

Assuming the input voltage V_(IN) at input 2 is to be sampled as outputvoltage V_(OUT1) at output 4 ₁, switch S₁ closes to connect amplifier A₁to the capacitor C₁ and the input of amplifier AMP₁. The voltage atV_(IN) is sampled onto capacitor C₁ and the buffered voltage appears onV_(OUT1). Then the switch S₁ is opened. The hold capacitor C₁ retainsthe sampled voltage, and thus, the voltage at V_(OUT1) remains constantfor a period of time. In a similar manner, the input voltage V_(IN) atinput 2 can be connected using switch S₁ to sample and hold the inputvoltage V_(IN) using another one of the capacitors C₂–C_(N) and itscorresponding amplifier AMP₂–AMP_(N).

The undesirable effects of the analog demultiplexer of the configurationof FIG. 1 are as follows:

-   (1) The amplifiers A₁ and AMP₁–AMP_(N) all create a voltage offset    from the signal at V_(IN);-   (2) The amplifiers A₁ and AMP₁–AMP_(N) are all shown with a gain of    +1, but gain errors occur;-   (3) A pedestal voltage offset error occurs when the switch S₁ opens;    and-   (4) The output amplifiers AMP₁–AMP_(N) are NOT identical—Or the same    input voltage at V_(IN) generates a different output at each output    VOUT₁–VOUT_(N).

To improve the performance of analog demultiplexers, several approacheshave been used. These approaches are described to follow.

1^(st) Improvement

A first improvement over the analog demultiplexer of FIG. 1 is shown inFIG. 2. In operation, assuming the voltage V_(IN) at input 2 is to besampled as an output voltage V_(OUT1) at output 4 ₁, then switch S₁closes and connects the output of amplifier A₁ to capacitor C₁ and thenon-inverting input of amplifier AMP₁. At the same instant a secondswitch S₂ closes, connecting the output of amplifier AMP₁ to theinverting input of amplifier A₁. Note components carried over from FIG.1 to FIG. 2 are similarly labeled, even though they are connected in adifferent manner, as will be components carried over into subsequentfigures. The equivalent circuit for this switch state for FIG. 2 isshown in FIG. 3.

With feedback from output amplifier AMP₁ to A₁, the equivalent circuitis assumed to have a unity gain configuration. Assuming that the circuitis stable and the gain of both amplifier A₁ and amplifier AMP₁ are verylarge, any offset of AMP₁ is divided down by the gain of A₁. The voltageV_(IN) plus the offset of amplifier A₁ is sampled onto the holdcapacitor C₁. So,V _(OUT1) =V _(IN) +Vos(offset of A ₁)

Advantages of the configuration of FIG. 2 are as follows:

-   (1) The voltage offset of AMP₁ is divided down by the gain of A₁;    and-   (2) The gain error or AMP₁ is divided down by the gain of A₁.

Undesirable effects of the configuration of FIG. 2 are as follows:

-   (1) The voltage offset of amplifier A₁;-   (2) A voltage offset caused by charge injection of switch S₂ when it    opens;-   (3) The gain error of amplifier A₁; and-   (4) A long settling time after switch S₂ closes.

Before switch S₂ of FIG. 2 closes, amplifier A₁ would be in an open loopconfiguration. Thus, its output will be in an undetermined voltagestate. Amplifier A₁ is “saturated”. Amplifier A₁ returns into its“active” region by glitching and ringing its output before it settles.(Settling time depends on the Bandwidth and Phase Margin of the cascadedamplifiers). When the output of amplifier A₁ rings, so does V_(OUT1), anundesirable effect.

2^(nd) Improvement

A second improvement over the analog demultiplexer of FIG. 1 is shown inFIG. 4. In the circuit of FIG. 4, a hold capacitor C₁, C₂, etc. isplaced between the inverting input and output of each of the outputamplifiers AMP₁, AMP₂, etc. Switches S₁ and S₂ operate as a pair toconnect one of the output amplifiers AMP₁, AMP₂, . . . between theoutput of amplifier A₁ and its non-inverting input. A switch S₃ connectsthe output of A₁ to a reference voltage V_(REF) when the switches S₁ andS₂ are not connected. The non-inverting input of the output amplifiersAMP₁, AMP₂, . . . are likewise connected to the reference V_(REF).

In operation it is first assumed that V_(IN) is to be sampled toV_(OUT1). Switch S₁ then closes and connects the output of amplifier A₁to capacitor C₁ and the inverting input of amplifier AMP₁. At the sameinstant, switch S₂ closes, connecting the output of amplifier AMP₁ tothe non-inverting input of amplifier A₁. Switches S₁ and S₃ arenon-overlapping, or are not connected at the same time. The equivalentcircuit of such a connection is shown in FIG. 5.

With feedback, the circuit is in a unity gain configuration. If the gainof amplifier A₁ and AMP₁ are large, thenV_(OUT1)˜V_(IN)+Vos1 (offset of amplifier A₁).

With amplifier AMP₁ in a feedback path, its inverting input (which isalso the output of amplifier A₁) is approximately equal to V_(REF). Forthis unity-gain configuration to settle fast, both sides of switch S₁have to be approximately V_(REF) before switch S₁ closes.

So, the output of the amplifier A₁ should be approximately at V_(REF)before switch S₁ closes. This is done by clamping the output of A₁ toV_(REF) by turning on switch S₃ (note: switch S₁ and S₃ arenon-overlapping). This ensures that amplifier A₁ stays in the “active”region resulting in a faster settling time.

Advantages of the configuration of FIG. 4 are as follows:

-   (1) The voltage offset of AMP₁ is divided down by the gain of A₁,    and is negligible.-   (2) The settling time is reduced (Voltage at both sides of switch S₁    are approximately the same and amplifier A₁ is in its active region    when switch S₁ closes).-   (3) The gain error of AMP₁ is divided down by the gain of A₁.

Undesirable effects of the configuration of FIG. 4 are as follows:

-   (1) The voltage offset of amplifier A₁ remains;-   (2) The gain error of amplifier A₁ remains; and-   (3) Charge injection of switch S₁ to the output capacitor causing an    offset error on the output.

SUMMARY

In accordance with an embodiment of the present invention, an analogdemultiplexer is provided with the voltage offset and gain error ofamplifiers AMP₁–AMP_(N) and A₁ divided down to a minimal value. Further,the analog demultiplexer has a minimal settling time, and chargeinjection from switch S₁ to the output generates a minimal offset error.

The analog demultiplexer in accordance with an embodiment of the presentinvention (referring to FIG. 6) includes an input amplifier A₁, and aplurality of output amplifiers AMP₁–AMP_(N), similar to FIG. 2. Theoutput and inverting (−) input of amplifiers AMP₁–AMP_(N) are connectedby a respective capacitor C₁–C_(N), as in FIG. 2. Also, similar to FIG.2, a switch S₁ (in the case of FIG. 6 multiple switches S_(1a), S_(1b),etc.) serve to connect the output of amplifier A₁ to the inverting inputof a respective one of amplifiers AMP₁–AMP_(N). Similar to FIG. 2, aswitch S₂ (in the case of FIG. 6 multiple switches S_(2a), S_(2b), etc.)serve to connect the output of one of amplifiers AMP₁–AMP_(N) to thenon-inverting input of the amplifier A₁. As in FIG. 2, switches S_(2a),S_(2b), etc. can function to switch together with respective ones ofswitches S_(1a), S_(1b), etc. As in FIG. 2, with feedback from theoutput of amplifiers AMP₁–AMP_(N) through A₁, the gain as well as theoffset of any of AMP₁–AMP_(N) is divided down by the gain of A₁.

Unlike the circuit of FIG. 2, in an embodiment, the amplifier A₁ has acapacitor C_(S1) connected to its non-inverting input and anothercapacitor C_(S2) connected to its inverting input. A switch S₅₀ connectsthe inverting input of amplifier A₁ to its output, and a switch S₄₀connects the non-inverting input of amplifier A₁ to a voltage referenceV_(REF) matching a voltage reference V_(REF) applied to thenon-inverting input of amplifier AMP₂. A switch S₃₀ connects thecapacitor C_(S1) to receive the demultiplexer input 2, while a switchS₃₅ connects the capacitor C_(S2) to the demultiplexer input 2. Inoperation, switches S₄₀, S₅₀, S₃₀ and S₃₅ are initially closed, whileswitches S_(2a), S_(2b), etc. are open to charge up both capacitorsC_(S1) and C_(S2) to V_(REF) to assure both inputs of amplifier A₁ andits output are at V_(REF). Switch S₅₀ provides feedback to assure gainerrors and offset of A₁ are divided down. Switches S₃₀, S₃₅, S₄₀ and S₅₀are then open, while one of switches S_(2a), S_(2b), etc. is closed incorrespondence with a switch S_(1a), S_(1b), etc. Since the inputs andoutput of both A₁ and the corresponding amplifier AMP₁–AMP_(N) willinitially be at V_(REF), very little settling time will be required tostabilize the respective output voltage V_(OUT1)–V_(OUTN).

To improve switching speed in one embodiment, the switches S_(1a),S_(1b), etc. are preferably formed from as a CMOS switch made from acombined PMOS and NMOS transmission gate. The NMOS transistor enablesthe circuit to switch fast, while the PMOS transistor being on after thecircuit settles removes voltage offset typically existing with only anNMOS transistor. Using a CMOS switch, in one embodiment a dummy switchcan be added in series with the CMOS switch which is half the size tocancel any charge offset produced by the active switch. In anotherembodiment, the gate size of transistors for switches S_(1a), S_(1b)etc. are reduced to limit any offset due to these switches.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details of the present invention are explained with the help ofthe attached drawings in which:

FIG. 1 shows one conventional configuration for an analog demultiplexer;

FIG. 2 shows a first improvement over the analog demultiplexer of FIG.1;

FIG. 3 shows an equivalent circuit for the switch state of FIG. 2;

FIG. 4 shows a second improvement over the analog demultiplexer of FIG.1;

FIG. 5 shows an equivalent circuit for the switch state of FIG. 4;

FIG. 6 shows an analog demultiplexer in accordance with the presentinvention;

FIG. 7 shows the analog demultiplexer of FIG. 7 with connections onlybetween the input amplifier A₁ and output amplifier AMP₁.

FIG. 8 shows an equivalent circuit for the switch state of FIG. 7.

FIG. 9 shows the equivalent circuit for FIG. 7 with switches S₄₀ and S₅₀changing to an open state;

FIG. 10 shows the equivalent circuit for FIG. 7 with the S₄₀ and S₅₀ ofFIG. 9 remaining open and additionally switches S₃₀ and S₃₅ opening;

FIG. 11 shows an equivalent circuit for FIG. 7 with the switches S₃₀,S₄₀, S₅₀ remaining open, but switches S_(2a) and S_(1a) closing;

FIG. 12 shows an equivalent circuit with switches S₃₀, S₄₀, S₅₀remaining open, and switch S_(2a) remaining closed, but S_(1a)reopening;

FIG. 13 shows transistors used to create a switch S_(1a), and voltagesapplied to reduce any offset due to charge injection; and

FIG. 14 shows components for an embodiment of the input amplifier A₁.

DETAILED DESCRIPTION

An approach for an analog demultiplexer in accordance with the presentinvention is shown in FIG. 6. Using this circuit and switching S_(1a),S_(1b) . . . etc. and S_(2a), S_(2b) . . . etc., control logic can guideV_(IN) to be sampled and held on a specific one of the output buffersAMP₁–AMP_(N). Note that FIG. 6 shows use of multiple switches S_(1a),S_(1b) . . . etc. and S_(2a), S_(2b) . . . etc., as an alternative, asingle switch could be used for all of switches S_(1a), S_(1b) . . .etc. or S_(2a), S_(2b) . . . etc. However, use of multiple switchespermits the input amplifier A₁ to be connected to more than one of theoutput amplifiers AMP₁–AMP_(N) at one time. Further note that althoughswitches such as S_(1a) and S_(2a) typically open and close togethersimultaneously in prior art designs, in the present invention theswitches may or may not close simultaneously.

For a description of operation, to simplify the system of FIG. 6, FIG. 7is included showing only two amplifiers, assuming V_(IN) is to besampled to an output amplifier AMP₁. Further, it is initially assumedthat the gain of amplifier A₁=A₁ and the gain of amplifier AMP₁=A₂. Theconnection of switches in FIG. 7 enable the value V_(REF) to bemaintained at the inputs and output of amplifiers A₁ and AMP₁–AMP_(N)prior to connection of the amplifier A₁ to one of amplifiersAMP₁–AMP_(N) is described to follow with equivalent circuits shown foreach stage.

1^(st) Stage

First, switches S₄₀, S₅₀, S₃₀ and S₃₅ are closed, making the circuitportion shown in FIG. 7 appear as shown in the equivalent circuit ofFIG. 8. Amplifier A₁ is in a unity-gain configuration. Amplifier AMP₁ isin the “hold” state, keeping the previously set V_(OUT1) constant. Thus,the following applies. $\begin{matrix}{{Vx} = {{A1}\left( {V_{+} + V_{OS1} - V_{-}} \right)}} \\{= {{A1}\left( {V_{REF} + V_{OS1} - {Vx}} \right)}} \\{{{Vx}\left( {1 + {A1}} \right)} = {{A1}\left( {V_{REF} + V_{OS1}} \right)}} \\{{Vx} = {\left\lbrack {{A1}/\left( {1 + {A1}} \right)} \right\rbrack\left( {{Vref} + V_{OS1}} \right)}} \\{{{Voltage}\mspace{14mu}{across}\mspace{14mu}{capacitor}\mspace{14mu} C_{S1}} = V_{CS1}} \\{= {V_{IN} - V_{REF}}} \\{{{Voltage}\mspace{14mu}{across}\mspace{14mu}{capacitor}\mspace{14mu} C_{S2}} = V_{CS2}} \\{= {V_{IN} - V_{X}}} \\{= {V_{IN} - {\left\lbrack {{A1}/\left( {1 + {A1}} \right)} \right\rbrack{\left( {V_{REF} + V_{OS1}} \right).}}}}\end{matrix}$2^(nd) Stage

Next, switches S₄₀ and S₅₀ are opened creating a circuit as shown inFIG. 9. When switches S₄₀ and S₅₀ are opened, there is charge injectedinto capacitors C_(S1) and C_(S2). The offset would be common mode ifS₄₀/C_(S1)˜S₅₀/C_(S2). Assuming the size of switches S₄₀=S₅₀ andC_(S1)=C_(S2), the offset to both capacitors caused by charge injectionwould be the same.

3^(rd) Stage

Next, in addition to the switches open in FIG. 9, switches S₃₀ and S₃₅are opened creating a circuit as shown in FIG. 10. As a further optionin this state, switch S_(1x) can be closed, connecting V_(X) to V_(REF),so V_(X) is clamped to V_(REF). Switch S_(1x) is then opened beforestage 4.

4^(th) Stage

Next, switches S_(1a), S_(2a) and S₃₅ are closed creating a circuit asshown in FIG. 11. As configured in FIG. 11, the equations of Appendix Iof this application apply.

5^(th) Stage

Next, switch S_(1a) is reopened as shown in FIG. 12, as the amplifierAMP₁ has sampled and will hold the value V_(IN) at the output V_(OUT1).

6^(th) Stage

Next, or in conjunction with switch S_(1a), switch S_(2a) is reopened,to prepare for a subsequent sampling since V_(IN) has been sampled andheld by output amplifier AMP₁. The control logic can now start to sampleV_(IN) to a different amplifier (for example AMP₂). With sampling toAMP₂, all the stages explained herein are then performed again, but withAMP₂ replacing AMP₁. After V_(IN) is sampled to AMP₂, the control logicsamples V_(IN) to another amplifier and so on. To overcome voltagedroop, the output amplifiers AMP₁–AMP_(N) are refreshed repetitively bya subsequent sampling of V_(IN).

The advantages of the configuration in accordance with the presentinvention are as follows:

-   (1) The offset for both amplifier A₁ and AMP₁ are reduced by the    gain of A₁;-   (2) The circuit settles fast because both sides of switch S_(1a) are    almost at the same potential before switch S_(1a) closes; and-   (3) CMRR and gain error for both amplifiers are corrected.

To improve the charge injection in switch S_(1a), the followingadditional steps can be performed:

-   (1) Use a small switch; and-   (2) Use charge injection cancellation techniques like:    -   in CMOS, use PMOS and NMOS transmission gates; and    -   use a dummy switch.

Use of small switch, simply implies use of one or more transistorsmaking up the switch with a small gate size. The smaller gate sizereduces charge buildup, and thus charge injection when the switch opensor closes. Typically, a high voltage transmission gate is large indimension to withstand the higher voltage applied on it. Due to thelarge gate size, a large charge will be lying underneath the gate whenit is in its “on” state. When the switch opens, the charge will injectinto the hold capacitor creating an offset seen on the output amplifier.The voltage driving the transmission gate switches will be between ahigh voltage and ground. The large voltage swing on the transmissiongate feeds through to the hold capacitor through the overlap capacitanceof the large switch, providing another source offset.

Use of CMOS designs enables reduction in charge injection since it usesPMOS transistors causing less charge buildup. The CMOS design stillincludes an NMOS transistor to which turns on initially much faster thanthe PMOS transistor. In CMOS high voltage designs, charge injection willstill produce an offset in the hold capacitors of the output amplifiers.The offset is caused by the charge under the gate injecting into thehold capacitor when the switch opens. The amount of offset is determinedby: (1) the control voltage swing of the switch; and (2) the size of theswitch.

A low voltage CMOS switch 10 used for switch S_(1a) includes PMOS andNMOS transistors 11 and 12 as shown in FIG. 13. The source-drain path ofthe NMOS transistor 11 and PMOS transistor 12 are connected in parallelbetween the output of amplifier A₁ and an input of amplifier AMP₁. Thegates of transistors 11 and 12 receive complementary control signals φand φbar.

To avoid offset, particular control voltages as well as use of a dummyswitch may be employed as further illustrated in FIG. 13. In theapproach of FIG. 13, two supply voltages are used for amplifier A₁.(Vdd=High voltage; V1d=low voltage). The output of amplifier A₁ isprevented from going above V1d (output of amplifier A1 can swing betweenVss1 and V1d; Note: Vss1 and Vss could be tied together). The dummyswitch 15 has transmission gates half the size of the transmission gatesof transistors 11 and 12 forming the low voltage switch 10. Thetransmission gates of the dummy switch 10 are driven by a signal φ andφbar, similar to switch 10. Signals φ and φbar swing between voltages ofV1d and Vss1. The output of amplifier A₁ is prevented from going aboveV1d so that a low voltage switch 10 and dummy switch 15 can be used forswitch S_(1a).

By using a low voltage switch (small gate area—small charge under thegate), the offsets caused by charge injection and clock feed through canbe further minimized. The dummy switch 15 that is half the size ofswitch 10 is used to cancel the charge produced by switch 10.

Another improvement is having the value of V_(REF) between V1d and Vss.When the circuit settles in the unity gain configuration, the output ofamplifier A₁ would be at V_(REF). The chosen V_(REF) voltage isdependent on the size of the PMOS and NMOS transistors in switch S_(1a).If the PMOS and NMOS transistors in switch S_(1a) are the same size, thecharge in both the transistors (holes recombining with the electrons)would cancel each other out if:V _(REF)=(V 1 d+Vss)/2.   (1)

An example of a circuit implementation of amplifier A₁ is shown in FIG.14. Amplifier A₁ includes two PMOS transistors 21 and 22 connected in adifferential fashion. Transistor 21 has a gate forming the inverting (−)input of amplifier A₁, while the gate of transistor 22 forms thenon-inverting (+) input of amplifier A₁. The sources of transistors 21and 22 are fed from a current sink 20 connected to Vdd. Drains oftransistors 21 and 22 are connected through respective NMOS transistors24 and 25 to Vss. Note Vss and Vss1 are the same voltage. Transistors 24and 25 are then connected in a current mirror configuration withrespective NMOS transistors 27 and 28. Transistor 27 has a source-drainpath connected in series with transistor 30 between V1d and Vss1, whiletransistor 28 has a source-drain path connected in series withtransistor 31 between V1d and Vss1. The connection between thesource-drain paths of transistors 28 and 31 form the output of theamplifier A₁.

Although the present invention has been described above withparticularity, this was merely to teach one of ordinary skill in the arthow to make and use the invention. Many additional modifications willfall within the scope of the invention, as that scope is defined by theclaims which follow.

1. A method for demultiplexing an input signal (V_(IN)) using an inputamplifier (A₁) and a plurality of output amplifiers (AMP₁–AMP_(N)), theinput amplifier (A₁) having first and second inputs and an output, theoutput amplifiers (AMP₁–AMP_(N)) each having first and second inputs andan output, the method comprising the steps of: providing a first inputcapacitor (C_(S1)) having a first terminal, and having a second terminalconnected to the first input of the input amplifier (A₁); providing asecond input capacitor (C_(S2)) having a first terminal, and having asecond terminal connected to the second input of the input amplifier(A₁); accepting the input signal (V_(IN)) at an input terminal (2);selectively connecting the input terminal (2) to the first terminal ofthe first input capacitor (C_(S1)); selectively connecting the inputterminal (2) to the first terminal of the second input capacitor(C_(S2)); selectively connecting the output of the input amplifier (A₁)to the first input of one of the output amplifiers (AMP₁–AMP_(N)); andselectively connecting the output of one of the output amplifiers(AMP₁–AMP_(N)) to the first terminal of the first input capacitor(C_(S1)).
 2. The method of claim 1, further comprising providingfeedback capacitors (C₁–C_(N)), each feedback capacitor connecting thefirst input of one of the output amplifiers (AMP₁–AMP_(N)) to itsoutput.
 3. The method of claim 1, wherein the selective connecting isperformed such tat when the first input of one of the output amplifiers(AMP₁–AMP_(N)) is initially connected to the output of the inputamplifier (A₁), the output of said one of the output amplifiers(AMP₁–AMP_(N)) is simultaneously connected the first terminal of thefirst input capacitor (C_(S1)).
 4. The method of claim 1, furthercomprising selectively connecting the second input of the inputamplifier (A₁) to the output of the input amplifier (A₁).
 5. The methodof claim 4, further comprising selectively connecting the first input ofthe input amplifier (A₁) to a reference voltage (V_(REF)).
 6. The methodof claim 5, wherein the selective connecting is performed such that atthe same time: the first input of the input amplifier (A₁) is connectedto the reference voltage (V_(REF)), the second input of the inputamplifier (A₁) is connected to the output of the input amplifier (A₁),the input terminal (2) is connected to the first terminal of the firstinput capacitor (C_(S1)), and the input terminal (2) is connected to thefirst terminal of the second input capacitor (C_(S2)).
 7. The method ofclaim 6, wherein the selective connecting is performed such tat theoutput of none of the output amplifiers (AMP₁–AMP_(N)) is connected tothe first terminal of to first input capacitor (C_(S1)) when: the firstinput of the input amplifier (A₁) is connected to the output of theinput amplifier (A₁), the first input of the input amplifier (A₁) isconnected to the reference voltage (V_(REF)), the input terminal (2) isconnected to the first terminal of the first input capacitor (C_(S1)),and the input terminal (2) is connected to the first terminal of thesecond input capacitor (C_(S2)).
 8. The method of claim 1, furthercomprising providing a reference voltage (V_(REF)) to the second inputof each of the output amplifiers (AMP₁–AMP_(N)).
 9. The method of claim8, further comprising connecting the output of the input amplifier (A₁)to the reference voltage (V_(REF)) when the output of the inputamplifier (A₁) is not connected to the first input of any of the outputamplifiers (AMP₁–AMP_(N)).
 10. A method for demultiplexing an inputsignal (V_(IN)) using an input amplifier (A₁) and a plurality of outputamplifiers (AMP₁–AMP_(N)); the input amplifier (A₁) having an inverting(−) input, a non-inverting (+) input and an output, the outputamplifiers (AMP₁–AMP_(N)) each having an inverting (−) input, anon-inverting (+) input and an output, the method comprising the stepsof: providing a first input capacitor (C_(S1)) having a first terminal,and having a second terminal connected to the non-inverting (+) input ofthe input amplifier (A₁); providing a second input capacitor (C_(S2))having a first terminal, and having a second terminal connected to theinverting (−) input of the input amplifier (A₁); accepting the inputsignal (V_(IN)) at an input terminal (2); selectively connecting theinput terminal (2) to the first terminal of the first input capacitor(C_(S1)); selectively connecting the input terminal (2) to the firstterminal of the second input capacitor (C_(S2)); selectively connectingthe output of the input amplifier (A₁) to the inverting (−) input of oneof the output amplifiers (AMP₁–AMP_(N)); and selectively connecting theinverting (−) input of the input amplifier (A₁) to the output of theinput amplifier (A₁).
 11. The method of claim 10, further comprisingproviding feedback capacitors (C₁–C_(N)), each feedback capacitorconnecting the inverting (−) input of one of the output amplifiers(AMP₁–AMP_(N)) to its output.
 12. The method of claim 10, furthercomprising selectively connecting the output of one of the outputamplifiers (AMP₁–AMP_(N)) to the first terminal of the first inputcapacitor (C_(S1)).
 13. The method of claim 12, wherein the selectiveconnecting is performed such that when the inverting (−) input of one ofthe output amplifiers (AMP₁–AMP_(N)) is initially connected to theoutput of the input amplifier (A₁), the output of said one of the outputamplifiers (AMP₁–AMP_(N)) is simultaneously connected the first terminalof the first input capacitor (C_(S1)).
 14. The method of claim 10,further comprising selectively connecting the non-inverting (+) input ofthe input amplifier (A₁) to a reference voltage (V_(REF)).
 15. Themethod of claim 14, wherein the selective connecting is performed suchthat at the same time: the non-inverting (+) input of the inputamplifier (A₁) is connected to the reference voltage (V_(REF)), theinverting (−) input of the input amplifier (A₁) is connected to theoutput of the input amplifier (A₁), the input terminal (2) is connectedto the first terminal of the first input capacitor (C_(S1)), and theinput terminal (2) is connected to the first terminal of the secondinput capacitor (C_(S2)).
 16. The method of claim 15, wherein theselective connecting is performed such that no output of the outputamplifiers (AMP₁–AMP_(N)) is connected to the first terminal of thefirst input capacitor (C_(S1)) when the non-inverting (+) input of theinput amplifier (A₁) is connected to the reference voltage (V_(REF)),the inverting (−) input of the input amplifier (A₁) is connected to theoutput of the input amplifier (A₁), the input terminal (2) is connectedto the first terminal of the first input capacitor (C_(S1)), and theinput terminal (2) is connected to the first terminal of the secondinput capacitor (C_(S2)).
 17. The method of claim 10, further comprisingproviding a reference voltage (V_(REF)) to the non-inverting input (+)of each of the output amplifiers (AMP₁–AMP_(N)).
 18. The method of claim10, further comprising connecting the output of the input amplifier (A₁)to the reference voltage (V_(REF)) when the output of the inputamplifier (A₁) is not connected to the inverting input (−) of any of theoutput amplifiers (AMP₁–AMP_(N)).
 19. A method for demultiplexing aninput signal (V_(IN)) using an input amplifier (A₁) and a plurality ofoutput amplifiers (AMP₁–AMP_(IN)), the input amplifier (A₁) having firstand second inputs and an output, the output amplifiers (AMP₁–AMP_(N))each having first and second inputs and an output, the method comprisingthe steps of: providing a first input capacitor (C_(S1)) having a firstterminal, and having a second terminal connected to the first input ofthe input amplifier (A₁); providing a second input capacitor (C_(S2))having a first terminal, and having a second terminal connected to thesecond input of the input amplifier (A₁); accepting the input signal(V_(IN)) at an input terminal (2); and simultaneously connecting theinput terminal (2) to the first terminal of the second input capacitor(C_(S2)), the output of the input amplifier (A₁) to the first input ofone of the output amplifiers (AMP₁–AMP_(N)), and the output of said oneof the output amplifiers (AMP₁–AMP_(N)) to the first terminal of thefirst input capacitor (C_(S1)).
 20. The method of claim 19, whereinprior to said simultaneously connecting, causing the first and secondinputs and the output of the input amplifier (A₁) to be at or close to areference voltage level V_(REF) that is applied to the second input ofeach of the output amplifiers (AMP₁–AMP_(N)).